With the progress of the semiconductor process technology and the miniaturization of the microelectronic components, the density of semiconductor components on a single chip is gradually increased. Correspondingly, the spacing interval between every two adjacent semiconductor components is gradually decreased. Under this circumstance, the etching process for forming contact holes or dual damascene openings in a dielectric layer becomes more complicated.
For example, in a 45 nm generation semiconductor process, the pitch between every two adjacent contact holes could be smaller than a predetermined value, such as 155 nm, and the after development inspection critical dimension (ADICD) is about 70˜80 nm. In accordance with the current single exposure patterning (SP) photolithography technology, it is impossible to produce a contact hole of about 70˜80 nm diameter with a pitch smaller than 155 nm by a single exposure process. For solving the above drawbacks, a double patterning technology such as a litho-etch-litho-etch (LELE) process is employed to form a contact hole or a dual damascene opening.
A conventional litho-etch-litho-etch (LELE) process for forming the dual damascene opening will be illustrated in more details as follows. Firstly, a first hard mask layer with a trench pattern is formed on an inter-layer dielectric (ILD) layer. Then, a photoresist layer is filled into an opening of the trench pattern. Then, a second hard mask layer is formed on the photoresist layer. Then, two photo processes and two etching processes are performed to transfer via opening patterns to the second hard mask layer. By using the second hard mask layer as an etching mask, via openings are formed in the inter-layer dielectric layer. After the second hard mask layer is etched, another etching process is performed to form a trench opening. Meanwhile, the dual damascene opening is produced.
However, since the second hard mask layer is a silicon-containing hard mask bottom anti-reflection coating (SHB) layer, some drawbacks may occur. For example, during the process of transferring the photoresist pattern, the possibility of having resulting shrinkage of the critical dimension (CD) of the via opening pattern will be increased. Under this circumstance, the critical dimension of the overall dual damascene opening is possibly suffered from excessive variation. Furthermore, since the etching selectivity of the SHB layer is inferior to the inter-layer dielectric layer, the possibility of breaking through the inter-layer dielectric layer during the first etching process of forming the via opening is increased. Furthermore, during the process of removing the second hard mask layer, the particles generated by the photoresist layer and the SHB layer may result in contamination. Under this circumstance, the dielectric constant of the inter-layer dielectric layer exposed to the via opening is deteriorated.
Therefore, there is a need for providing an improved method of forming a dual damascene opening in order to obviate the drawbacks encountered from the prior art and increase the yield of the semiconductor device.